An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Omowuyi Olajide; Bashir Abdulrazaq; Adewale Adedokun; Ime Umoh; Akan Bello

doi:10.18495/comengapp.v9i3.345

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Affiliations

Omowuyi Olajide
Ahmadu Bello University

Bashir Abdulrazaq
Ahmadu Bello University

Adewale Adedokun
Ahmadu Bello University

Ime Umoh
Ahmadu Bello University

Akan Bello
Ahmadu Bello University

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An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Omowuyi Olajide ,
Bashir Abdulrazaq ,
Adewale Adedokun ,
Ime Umoh ,
Akan Bello

Vol 9 No 3 (2020)

DOI 10.18495/comengapp.v9i3.345

Submitted: Aug 4, 2020

Published: Oct 1, 2020

Abstract

Low-Density-Parity-Check (LDPC) based error control decoders find wide range of application in both storage and communication systems, because of the merits they possess which include high appropriateness towards parallelization and excellent performance in error correction. Field-Programmable Gate Array (FPGA) has provided a robust platform in terms of parallelism, resource allocation and excellent performing speed for implementing non-binary LDPC decoder architectures. This paper proposes, a high throughput LDPC decoder through the implementation of fully parallel architecture and a reduction in the maximum iteration limit, needed for complete error correction. A Galois field of eight was utilized alongside a non-uniform quantization scheme, resulting in fewer bits per Log Likelihood Ratio (LLR) for the implementation. Verilog Hardware Description Language (HDL) was used in the description of the non-binary error control decoder. The propose decoder attained a throughput of 10Gbps at 400-MHz clock frequency when synthesized on a ZYNQ 7000 Series FPGA.